Can Register Values Be Used To Access Array Values In Verilog

Pastel

How-do-you-do!

I take successfully made a first version of a signal generator, and now I would like to make it dual channel.
If I make an arbitrary signal table, and want to read information technology from 2 different points at the same fourth dimension, is information technology possible,
or do I have to setup 2 tables?
For case if I utilise one table, can I have access to 2 elements of an array at the aforementioned fourth dimension?

something like this

                              chan1 <= array[i]; chan2 <= array[i+stage];

Thanks for any hint.

Pastel

KlausST

Howdy,

If your array are individual registers or if it is a dual port SRAM you may acces them at the same time.

If your array is a simple SRAM architecture, so you lot tin't acces them at the same time
But usually SRAM is fast ... yous may read 2 items 1 after the other .... and you are free to process or output them at the aforementioned time, so it may have the same effect than reading them at the same time.

Klaus

BradtheRad

What y'all advise is feasible although it ways doing a calculation (i+stage) during each loop. This uses cpu cycles. Instead you probably want speed when generating waveforms. Therefore it'south efficient if you prepare all values beforehand so you lot don't use excessive cpu cycles. Commonly this ways creating two arrays, eg., chan1 and chan2.

vGoodtimes

You can synthesize arrays with many/multiple accesses. The tools will do something to make them work. In some cases this ways using a dual-port BRAM/DMEM primitive. In some cases it means duplicating the retentivity. In some cases it means falling back to a DMEM or even annals based implementation. The latter leads to large surface area, depression clock rates, and long build times. For best results, you should read the coding style guidelines for your synthesis tool. This should have guidelines for writing BRAM/DMEM based ROMs/RAMs. I don't recall whatsoever tool always added a pragma to ensure the tools infer a BRAM, so you'll need to double check your results.

Pastel

How-do-you-do!

Thanks for your replies.
In the meantime, I tried, and could accept the upshot I wanted.
I fabricated a table of 1024 16-bit values:
reg[15:0] sine[1023:0];
Then I made a script to fill them all, and if I admission sine and sin[i + stage], then I get a sine and a cosine
on the telescopic (I take wired MAX5875 DAC at the output of the FPGA).
So patently it doesn't eat "cpu cycles" and by the style, I'm not certain I was articulate plenty, information technology'south a verilog implementation,
not a C program, so at that place is no loop every bit such, there is only an always@(posedge clk) block, then yep, information technology's a kind of hardware
loop. And then I simply suppose the two signals are changing on the same clock only every bit I'm a existent beginner in the FPGA world, I'thou
non sure of anything.

What I become:
- The FPGA clock is at 100 MHz. But as I accept to ready the data, on clock rising edge, and then the DAC clock at the next
rising edge, then the DAC clock is fifty MHz, which should yield 50 MSamples per second. As the table length is 1024, and then
I should get l kHz or a little bit less.
- At the output, I tin encounter the sine and cosine signals of this unproblematic experiment. I was expecting 50M / 1024 = 48.828
kHz, only my sine waves are at 97 kHz, and I don't understand why for the time being.

Here is the core of what I'grand doing. I skip what I do with the LEDs, which is basically lighting them or not. So I send information to
the DAC, and I generate the corresponding clock. So on 1 rising border of clk, I check if the dac clock (max_clk) is 0, in which
example I strobe the input data by setting it to one. If it'southward already 1, I set the DA and DB to the DAC input and I rearm the clock
to 0 for the next clk ascension edge.

- Tin anybody explain me why I get 97 kHz instead of 48?
- Is in that location a way to put my sine array to a dedicated file and keep the top level object reasonably small-scale?

Thanks

Pastel

module test190803(DA, DB, max_clk, red_led, blue_led, clk) brainstorm output reg[15:0] DA, DB; // Data of the DAC output reg max_clk; // Clock of the DAC output reg red_led, blue_led; // Some leds for bank check; input clk; // FPGA 100 MHz input clock // Some variables reg[fifteen:0] sine[0:1023]; reg[9:0] sinindex; reg[ix:0] cosindex; // Initialization initial begin sin[0] = xxxxxx; // Long sequence of 1024 initializations sinindex = 0; cosindex = 256; end always@(posedge clk) begin // Increase the stage counters which volition automatically roll back to 0 afterward overflow. sinindex <= sinindex+1; cosindex <= cosindex+1; // Ready the dac clock loftier, or set the input data and set it low. if(max_clk == 0) begin max_clk <= i; end else begin DA <= Sine[sinindex]; DB <= Sine[cosindex]; max_clk <= 0; end end endmodule

- - - Updated - - -
Hello!

Distressing, I didn't observe your reply.
Ok, I'chiliad an accented beginner and I'm non sure of what I used. I just wrote some code, it works, more or less.
I don't know what is BRAM, DMEM... only to tell you how newbie I am...

Merely anyway, I'one thousand able to admission more than one element of an assortment at a time, and information technology doesn't do information technology sequencially
otherwise the frequency would drop, and information technology doesn't. The frequency is even twice what I calculated, and
I don't understand why (see full explanation above).

Thanks,

Pastel

FvM

why I go 97 kHz instead of 48?

Because you lot are incrementing the indexes every clock cycle. You want somethink like this.

                                                                                                                                                                          Lawmaking Verilog -                                        [aggrandize]                                                                          
                                  
                                                                                                                                                    one 2 three iv 5 6 7 8 nine ten 11                                        
                                                                                                                                                              e'er                                          @                                          (                                          posedge                                          clk)                                          brainstorm                                          if                                          (max_clk                                          ==                                          0                                          )                                          max_clk                                          <=                                          1                                          ;                                          else                                          begin                                          sinindex                                          <=                                          sinindex+                                          1                                          ;                                          cosindex                                          <=                                          cosindex+                                          1                                          ;                                          max_clk                                          <=                                          0                                          ;                                          cease                                          DA                                          <=                                          Sine[sinindex]                                          ;                                          DB                                          <=                                          Sine[cosindex]                                          ;                                          terminate

- - - Updated - - -

Is there a way to put my sine assortment to a dedicated file and keep the top level object reasonably minor?

Many ways. E.1000. using a binary or hex file and $readmemb or $readmemh. Or calculating the initialization values at compile time using $sin() and $cos() organisation functions. Or write a function that delivers the values.

vGoodtimes

@Pastel: DMEM/BRAM are Xilinx's names for "distributed memory" and "block ram". Intel also has similar blocks. BRAM requires 1+ bicycle of read/write latency only is the most dense. DMEM allows async reads but is much less dense. when all else fails the tools take to employ registers and muxes. Your blueprint looks similar it should be using BRAM as the table is big enough and yous don't do annihilation that would prevent this.

Pastel

Hello!

Thanks for your reply!
And for the solution! It was really a light-headed question. Indeed, I was incrementing at every pace.
It works now.

Past the way, I have asked a few times, but how tin can I format the code with colored syntax?
Is it something merely moderators can do?

Thanks,

Pastel

- - - Updated - - -

Hello!

Thanks for your reply!

BRAM requires 1+ cycle of read/write latency simply is the nigh dense.

As far as I can tell, there is not much latency. The clock spins at 100 MHz, and I tin can output samples at 50 Ms/s.
So yes, one cycle to put the information at the DAC input, and the side by side cycle to latch it. But I call up it'due south the least I can practise
to keep the timing prophylactic.

Your pattern looks like it should be using BRAM equally the tabular array is large enough and yous don't do anything that would prevent this.

Only to be sure (not english native, sorry). You mean that my design is currently not using BRAM and I
should change it and so that it uses BRAM?
Or you mean that looking at the lawmaking, information technology'due south likely that my blueprint really uses BRAM?

the tabular array is big enough and you don't do annihilation that would forestall this.

To forbid the table to be big, or to prevent my design to employ BRAM?

By the way, I have some other question. I'k using the MAX5875 DAC which tin work at 200 Msps.
I take noticed that any I do, it works. I mean: this works:

                                                              if(max_clk == 0) begin             max_clk <= i;         end         else begin             DA <= Sine[sinindex];             DB <= Sine[cosindex];             max_clk <= 0;         terminate

And this also works:

                                                              if(max_clk == 0) begin             DA <= Sine[sinindex];             DB <= Sine[cosindex];             max_clk <= 1;         finish         else begin              max_clk <= 0;         end

I suppose that if I fix the clock and the data at the aforementioned time, there is anyhow a
delay between the information and the clock, so it works. In one case, the information is latched
immediately, and in the other case, the information from the previous cycle is latched.
There is no departure in matters of noise at the DAC output.
Can anybody tell me why it works in both case (is my explanation right)?

Thanks,

Pastel

vGoodtimes

Or you mean that looking at the lawmaking, it's probable that my design really uses BRAM?

I wait the tools to implement your table in BRAM. This is desirable in this case. You should confirm this in synthesis logs -- the tools sometimes do unexpected things.

FvM

As for clock to data timing, you should review the MAX5875 specification. The information input must be stable during a window about 0.5 to 2 ns after rising clock edge. In and then far both clock phase settings you tried will typically work.

Information technology's however not preferred to generate the DAC clock in logic like you lot practise. Yous'll ameliorate use a crystal or PLL generated clock through a defended FPGA clock output. If your application purpose is synthesis of clean RF signals, e.grand. for a software defined radio or exam generator, y'all'll fifty-fifty prefer a crystal oscillator straight clocking the DAC for minimal phase noise. FPGA clock jitter is relative large.

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Verilog: read two values from an array at the same fourth dimension.

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